Role : System Validation Engineer (Pre & post)
Location : hyderabad
Preferred : Immediate to 30 days notice
Experience: 5 - 6 years
Expert-level C Language (8+/10) & Data Structures.System Validation on Pre & Post Silicon.Any prior knowledge of PCIe, CXL, NVME or USB will be a plus but not must.Interested can apply here or share cvs to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read LessJob Title: Lead DFT Engineer
Experience: 7+ Years
Location: Bangalore
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
Job Summary:
We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as:Synopsys: DFT Compiler, TetraMAX, TestMAXSiemens EDA: Tessent ScanPro, MBIST, IJTAGCadence/others: Modus, Encounter TestStrong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:
Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?
Lead DFT for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
Read Less