Job Title: Payroll SME / Consultant - APAC & EMEA Transition (ADP Celergo)
Location: Mumbai (Onsite - 4-5 days/week)
Duration: 5-6 Months Contract
Start Date: Immediate
Project Overview
We are seeking an experienced Payroll SME / Consultant to support a global payroll transition project across EMEA and APAC regions.
The role involves reviewing, standardizing, and transitioning payroll processes to a centralized payroll team in India, ensuring compliance, accuracy, and process efficiency.
Countries in Scope
EMEAAPACMust-Have Primary Skills
ADP Celergo (Mandatory): Hands-on experience in global payroll processing and implementation using ADP CelergoGlobal Payroll Expertise (EMEA & APAC): Strong knowledge of multi-country payroll operations, including statutory compliance and tax regulationsPayroll Transition / Migration Experience: Proven experience in transitioning payroll operations across regions or to shared service centersSOP Review & Process Standardization: Experience in reviewing, creating, and optimizing payroll SOPs to align with best practicesPayroll Compliance & Regulatory Knowledge: Deep understanding of country-specific payroll laws, tax filings, and statutory reportingKnowledge Transfer & Training: Ability to train and upskill payroll teams, including conducting parallel runs and validationsStakeholder Management: Experience working with global teams, Total Rewards, HR, and finance stakeholdersQuality Validation / Parallel Runs: Hands-on experience in payroll validation, reconciliation, and parallel run execution Read LessWe're Hiring: Protocol Testers Bangalore
We are currently looking for Protocol Testers to join our team at Bangalore.
Immediate joiners are highly preferred.
Experience Required: 4+ Years
Job Location: Bangalore (Onsite)
Interview Process
Face-to-Face InterviewCandidates must be willing to attend interviews in BangaloreKey Responsibilities & Skills:
Expertise in VoIP protocol testing, including SIP, RTP, and RTCP
Strong understanding of protocol behavior, signaling, and call flows
Experience in testing and validating communication protocol implementations
Ability to design and execute comprehensive protocol test cases
Familiarity with network packet analysis tools (e.g., Wireshark)
Good problem-solving and debugging skills
️ Please apply only if you are interested and available for a face-to-face interview at the Bangalore location.
How to Apply
Interested candidates can share their updated CV to:
Kindly share or tag relevant profiles who may be a good fit. Thanks!
Read LessLead - Design Verification (ODC Head & Individual Contributors)
Experience: 12 - 30 Years
Location: Bangalore - IBC Knowledge Park, Bannerghatta Road
Notice Period: Strictly 30 Days or Less
Role Summary
We are looking for a Senior Design Verification Leader to establish and scale an Offshore Development Center (ODC) f
This role requires a strong blend of:
Deep hands-on verification expertiseODC setup & delivery ownershipStrong customer handlingCross-functional program leadershipThe candidate will anchor complete verification execution for high-performance AI SoCs / accelerator designs.
Key Responsibilities
Set up and scale Verification ODC in BangaloreOwn end-to-end SoC/IP verification strategy and executionDefine verification methodology (UVM-based, coverage-driven, formal where required)Drive test plan creation, coverage closure, regression strategyEnsure signoff metrics (functional, code, assertion, toggle coverage)Act as primary technical interface to customerWork closely with Architecture, RTL, PD, DFT, and Software teamsManage hiring, mentoring, and scaling of 5-20+ verification engineersRequired Experience & Skills
12-30+ years in ASIC / SoC Design VerificationStrong expertise in SystemVerilog, UVMExperience in SoC-level verification of complex designsVerification for chips involving Must MIPI CSI, DSI, and SerDes protocols.
Ideal Candidate Profile
Hands-on technical leader (not purely managerial)Strong in customer communication & technical presentationsExperienced in ODC setup and offshore delivery ownershipStrong execution mindset with risk mitigation capabilityAble to build scalable, process-driven verification teams Read LessAbility to work on highly complex problems and provide feasible solutions in time.
Ready to work in 24 7 environments.Designing, developing, implementing, and maintaining a data warehouse to collate and integrate current/historical data from various sources/systems within an organizationImplementing procedures for maintenance, monitoring, backup, and recovery for the data warehouse and related systems Expertise in Dimensional Modelling (using Star / Snowflake schema) and drafting High Level and Low Level DWH DesignLess than 5 Yrs experience please do not expect revert .Immediate to 30 days joiner or serving NP required . Read LessBachelor's degree in Science, Engineering, or related field.
• 7+ years ASIC design, verification, or related work experience.
• At least 5 years of experience with the ISO 26262 / IEC 61508 standard including hands-on experience with Failure Modes and Effect Analysis (FMEA), Fault Tree Analysis (FTA) and Failure Modes Effect and Diagnostic Analysis (FMEDA)
• Proven experience in development of automotive SoC including VLSI design and methodology practices.
• Familiarity with Synopsys Functional Safety tools
• General knowledge in ASIC design process, digital design concepts, design verification tools and techniques, SoC architecture, etc.
• Prior automotive experience in ADAS and self-driving systems will be an advantage.
Design verification experience (developing test plan, test bench, tests, assertions, functional and code coverage, and debugging tests and designs)
• Knowledge of SoC, ARM processor, AMBA bus, DDR, or peripherals is desirable
Read LessPosition: Jira Admin
Exp: 5+ yrs
Location: Pune
Roles and Responsibilities:
Skills and Experience
Proven hands-on experience as a Jira admin managing large-scale environments (100+ projects, 2,000+ users, 50+ plugins).Extensive knowledge of project configuration, workflow automation, permission schemes, and plugin management.Demonstrated experience integrating Jira with Atlassian suite tools and external platforms (Qtest, Slack, GitHub).Strong dashboarding, reporting, and metric-setting abilities for compliance and audit requirements.Excellent troubleshooting, documentation, and user support skills.Effective communication, teamwork, and multitasking capabilities, handling requests efficiently and politely.Experience producing user guides, conducting training, and managing user onboarding. Read LessExperience: 5 - 15 years
Location : Hyderabad
Required Experience
Job Description:
Title: DDR and SOC verification engineer
Experience: 4 to 8
Role and Responsibilities:
Responsible for DDR PHY verification at SoC level Execute Gate level simulations. Responsible for code coverage closureSkill Requirements:
Hands on experience in SV/UVM based testbench development. Good understanding of DDR protocol systm level scenarios in SOC DDR model integration into SOC, JEDEC spec understanding Basic knowledge in Bus protocols-APB,AHB,AXI Experience in debugging gate level simulations, low power simulations Good to have: Scripting knowledge in Python/Perl. Qualifications: B.Tech/B.E/M.Tech/M.E Read LessACL Digital is hiring for the below requirement
Position: PCB Layout Designer
Experience: 6 to 10 years
Work location: Whitefield, Bangalore, No WFH option.
Interested can drop cvs/references to
Key Skill Requirements:
• Individual project handling: The designer must be capable of handling individual projects from conceptualization to completion.
• Tool expertise: The PCB designer must demonstrate expertise in using the Cadence Allegro tool for PCB design and basic knowledge of schematic design using Allegro Concept HDL / Or CAD Capture are the added advantage.
• DFM and DFA knowledge: The designer should have a strong understanding of Design for Manufacturing (DFM) and Design for Assembly (DFA) principles.
• High-speed digital design experience: The PCB designer must possess hands-on experience in designing high-speed digital interfaces such as PCIe Gen5&6 and DDR5 and HDI layout design.
• Knowledge in footprint creation: The designer should be proficient in creating component footprints according to industry standards.
• Best case analysis skill: The PCB designer must be proficient in best case analysis to proactively identify and mitigate potential design issues.
• Collaboration and communication: The PCB designer must possess excellent communication skills and be able to effectively collaborate with team members and stakeholders.
Read LessDFT Lead with Synopsys Tools
Work Location - Bangalore
Experience - 10+ Years
Desired Skills and Experience -
10+ years of experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
DFT logic integration and verification.
Experience in debugging low coverage and DRC fixes
Gate Level ATPG simulation with and without timing.
Pattern generation, verification, and delivery to ATE team.
Post silicon debug and support on failing patterns.
Good experience with tools from Synopsys like TestMAX
Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
Excellent problem-solving and debugging skills. Proactive in nature.
Leading junior teams, Mentoring/Training, and Project leadership.
Exp : 10+ yrs
Kindly Share/Refer
Read Less