RTL Design Engineer (SDC Constraints)
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We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.
Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems
Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)
Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure
Perform RTL quality checks, linting, and CDC analysis
Support timing debugging and constraint optimization across multiple design iterations
Participate in architecture discussions and design reviews
Ensure deliverables meet performance, power, and area (PPA) goals.
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️ 7+ years of hands-on experience in RTL ASIC design
️ Strong and mandatory expertise in SDC
️ Clocking strategies
️ Timing exceptions
️ Constraint validation and debug
️ Proficiency in Verilog/SystemVerilog
️ Solid understanding of ASIC design flow (RTL Synthesis STA P&R)
️ Experience working with Synopsys tools (DC, PrimeTime - preferred)
️ Strong knowledge of timing concepts and timing closure
️ Excellent debugging and problem-solving skills
Experience in low-power design techniques
Exposure to CDC/RDC methodologies
Experience with complex SoC designs
Scripting knowledge (Tcl / Perl / Python)
Prior experience working with global or distributed teams
Read LessJob Title: Design Verification Lead
Location: Bangalore/Hyderabad
Experience: 7+yrs
Job Type: Full-time
Industry: Semiconductors / VLSI / EDA
Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE or related field
Job Description:
We are looking for a passionate and experienced Design Verification Lead to drive the verification of complex SoC/IP designs. The ideal candidate will have deep expertise in functional verification methodologies and will be responsible for managing a team, defining verification strategies, and ensuring high-quality silicon delivery.
Key Responsibilities:
Own and lead verification activities for IP or SoC-level designs.Define and execute the verification plan, test strategy, and coverage goals.Develop and manage verification infrastructure (testbenches, stimulus, checkers, etc.).Collaborate with RTL design, DFT, PD, and firmware teams.Mentor and lead a team of verification engineers.Perform reviews of testbenches, test cases, and coverage reports.Drive simulation-based verification using SystemVerilog, UVM.Track and report project progress and debug issues independently.Participate in regression setup and continuous integration for verification.Deliver high-quality verified RTL to meet tape-out schedules.Required Skills:
7+ years of experience in ASIC/FPGA verification.Strong expertise in SystemVerilog and UVM.Hands-on experience in developing complex verification environments.Good understanding of coverage-driven verification (functional and code).Experience with scripting languages (Perl/Python/Tcl).Knowledge of protocols like AXI, AHB, PCIe, USB, DDR, etc.Familiarity with formal verification is a plus.Strong debugging skills using waveform tools like DVE, VCS, or ModelSim.Prior experience in leading teams and driving project deliverables.Good to Have:
Experience in Emulation/FPGA prototyping.Exposure to low-power verification (UPF).Knowledge of verification IPs and reuse methodologies.Hands-on with gate-level simulations and performance verification.Soft Skills:
Excellent communication and interpersonal skills.Ability to lead and mentor junior engineers.Strong problem-solving and analytical thinking.Ability to work in cross-functional and global teams.Interested can share CV to
Read LessJob Title: Design Verification Lead
Location: Bangalore/Hyderabad
Experience: 7+yrs
Job Type: Full-time
Industry: Semiconductors / VLSI / EDA
Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE or related field
Job Description:
We are looking for a passionate and experienced Design Verification Lead to drive the verification of complex SoC/IP designs. The ideal candidate will have deep expertise in functional verification methodologies and will be responsible for managing a team, defining verification strategies, and ensuring high-quality silicon delivery.
Key Responsibilities:
Own and lead verification activities for IP or SoC-level designs.Define and execute the verification plan, test strategy, and coverage goals.Develop and manage verification infrastructure (testbenches, stimulus, checkers, etc.).Collaborate with RTL design, DFT, PD, and firmware teams.Mentor and lead a team of verification engineers.Perform reviews of testbenches, test cases, and coverage reports.Drive simulation-based verification using SystemVerilog, UVM.Track and report project progress and debug issues independently.Participate in regression setup and continuous integration for verification.Deliver high-quality verified RTL to meet tape-out schedules.Required Skills:
7+ years of experience in ASIC/FPGA verification.Strong expertise in SystemVerilog and UVM.Hands-on experience in developing complex verification environments.Good understanding of coverage-driven verification (functional and code).Experience with scripting languages (Perl/Python/Tcl).Knowledge of protocols like AXI, AHB, PCIe, USB, DDR, etc.Familiarity with formal verification is a plus.Strong debugging skills using waveform tools like DVE, VCS, or ModelSim.Prior experience in leading teams and driving project deliverables.Good to Have:
Experience in Emulation/FPGA prototyping.Exposure to low-power verification (UPF).Knowledge of verification IPs and reuse methodologies.Hands-on with gate-level simulations and performance verification.Soft Skills:
Excellent communication and interpersonal skills.Ability to lead and mentor junior engineers.Strong problem-solving and analytical thinking.Ability to work in cross-functional and global teams.Interested can share CV to
Read LessAbout the Role
Manage end-to-end NetSuite projects (ERP, CRM, OpenAir, custom modules).
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About the Role
Manage end-to-end NetSuite projects (ERP, CRM, OpenAir, custom modules).
Responsibilitie
.
Qualificatio
).
Required Ski
About the Role
Manage end-to-end NetSuite projects (ERP, CRM, OpenAir, custom modules).
Responsibilitie
.
Qualificatio
).
Required Ski
About the Role
Manage end-to-end NetSuite projects (ERP, CRM, OpenAir, custom modules).
Responsibilitie
.
Qualificatio
).
Required Ski
About the Role
Manage end-to-end NetSuite projects (ERP, CRM, OpenAir, custom modules).
Responsibilitie
.
Qualificatio
).
Required Ski
About the Role
Manage end-to-end NetSuite projects (ERP, CRM, OpenAir, custom modules).
Responsibilitie
.
Qualificatio
).
Required Ski
About the Role
Manage end-to-end NetSuite projects (ERP, CRM, OpenAir, custom modules).
Responsibilitie
.
Qualificatio
).
Required Ski
