Job Function
Work on Analog/Mixed-Signal Functional Verification for Analog/Mixed-Signal IPs, such as SERDES, Sensors and beyond. The candidate will work with digital design, analog design, analog behavioral modeling and other design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to the entire life cycle of AMS Functional Verification process, from understanding specification, test planning to coverage closure and post silicon debugging support, to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.
Skills/Experience
Quick learner with strong critical thinking and creative problem-solving skills.Solid knowledge in ASIC design process, digital design, and UVM-based design verification methodologies. Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers, and checkers development, to test suite building to meet functional and code coverage goals, 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc. Power-aware simulations and gate level simulations is a plus.Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus. Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus.Familiar with programming languages: C, C++, and/or SystemC is a plus.Responsibilities
Work in AMS IP Design Verification, in UVM-based verification environment. Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goalsApply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. Read LessPosition Overview:
We are seeking a highly skilled Design Verification Engineer with more than 5 years of experience, specializing in Display Interface protocols - specifically Display Port (DP/eDP) IP and subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, expertise in System Verilog (SV) programming & UVM Methodology, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.
Key Responsibilities:
Develop and implement comprehensive verification plans for DP/eDP and DP Tunnelling over USB4 IP and Subsystems.Create and maintain testbenches using System Verilog and UVM methodology.Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.Collaborate with designers and other cross-functional teams to understand design specifications and requirements for IP and subsystems.Identify and resolve design and verification issues, ensuring high-quality and robust designs.Generate and analyze verification metrics to track progress and ensure coverage goals are met.Participate in design and verification reviews, providing technical expertise and insights.Stay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.Mentor junior verification engineers and provide technical guidance.Qualifications:
Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.5+ years of experience in design verification, with a focus on display protocols such as DP, eDP, HDMI, and related IP verification.Knowledge of USB4 and any other memory protocols is a plus.Proficiency in verification languages and methodologies, such as System Verilog, UVM, and other industry-standard tools.Strong understanding of digital design concepts, RTL coding, and simulation.Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.Excellent problem-solving skills and attention to detail.Strong communication and teamwork skills, with the ability to work effectively in a collaborative environment.Proven track record of successfully verifying complex IP blocks and subsystems.Ready to make an impact in display technology? Apply now and join our team!
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